1. Field of the Invention
The present invention relates to a method for manufacturing a dynamic random access memory (DRAM), and more particularly to a method for manufacturing DRAM having a redundancy circuit region, which can obtain better controllability when the fuse is blown by a laser beam.
2. Description of the Prior Art
Referring to FIGS. 1A through FIG. 1H, the cross-sectional side views of a conventional method for manufacturing a DRAM having a redundancy circuit are depicted in sequence.
Referring now to FIG. 1A, a cross-sectional view of the starting semiconductor substrate 10 including a memory cell region I and a redundancy circuit region II is schematically shown. A field oxide 12 (FOX) is formed by using conventional local oxidation of silicon (LOCOS). Then, the gate electrode G and the spacer 19 are formed on the semiconductor substrate 10. Next, the silicon nitride thin layer 22 is formed on the upper surface and the side wall of the gate electrode G. The gate electrode G consists of the gate oxide 14, the polysilicon layer 16, polycide layer 18, and the silicon oxy-nitride layer 20.
Subsequently, the insulated layer 24, for example borophosphosilicate glass (BPSG), is formed by chemical vapor deposition (CVD). Then, the insulated layer 24 is selectively etched to form a hole, and a conductive material is filled into the hole so as to form the conductive contacts 26a, 26b, 26c. Afterward, the non-doped silicon glass (NSG) layer 28 is formed. Moreover, a complex layer of polysilicon and polycide is formed, then the complex layer is selectively etched to form the bit line B consisting of the polysilicon 32a and the polycide 34a in the memory cell region I, and the fuse F consisting of the polysilicon 32b and the polycide 34b in the redundancy circuit region II. The bit line B is electrically connected with the conductive contact 26b via the conductive plug 30.
Next, as shown in FIG. 1B, the insulated layer 36, for example silicon oxide, is now formed by high-density plasma chemical vapor deposition (HDPCVD), then polished by chemical mechanical polishing (CMP). The nitride layer 38 is then formed.
Now as shown in FIG. 1C, the capacitor contact hole 39 is formed. The capacitor contact hole 39 is etched open in the silicon nitride layer 38, the insulated layer 36, and the NSG layer 28 by photolithography techniques and anisotropic etching.
Referring now to FIG. 1D, the insulated layer 40 is deposited, for example by chemical vapor deposition (CVD). The preferred thickness of the insulated layer 40 is usually in the range from between about 8,000 to 12,000 angstroms.
Now as shown in FIG. 1E, the trench is formed by selectively etching the insulated layer 40 in the position above the contact hole 39 to expose the silicon nitride layer 38, and the insulated layer 40 filled in the contact hole 39 is removed at the same time. The conductive material 41 is filled in the contact hole 39, and the conductive material 42 is deposited all over the side wall and the bottom of the trench. The conductive material 42, for example is a polysilicon, and serves as a lower electrode of a crown capacitor.
Referring to FIG. 1F, the thin dielectric layer 44 is formed on the conductive material 42. The dielectric layer 44 is for example a complex layer of oxide/nitride/oxide (ONO). The conductive layer 46, for example a polysilicon layer, is then deposited.
Next, referring to FIG. 1G, the conductive layer 46 is patterned to form an upper electrode 46a of the capacitor in the memory cell region I, and an etching stop layer 46b in the redundancy circuit region II. Afterward, the oxide passivation layer 48 is formed to cover the upper electrode 46a and the etching stop layer 46b. The conductive line 54 is then formed on the oxide passivation layer 48, and is connected with the upper electrode 46a via the metal plug 52. The oxide passivation layer 50 is then formed over the oxide passivation layer 48.
Finally, as shown in FIG. 1H, by using the etching stop layer 46b as a stop layer, the oxide passivation layer 50 and 48 are etched to form a trench 56 above the fuse F in the redundancy circuit region II.
However, the distance D1 between the fuse F and the etching stop layer 46b as shown in FIG. 1H is too large. Therefore, the fuse F can not be easily blown by a laser beam. Furthermore, the laser beam can not pass through the etching stop layer 46b made of polysilicon, thereby causing increasing a step for removing the etching stop layer 46b before blowing the fuse F.